1. Field
The present disclosure generally relates to integrated circuits (ICs). More specifically, one aspect of the present disclosure relates to embedding 3D passive devices within an integrated interposer.
2. Background
The process flow for semiconductor fabrication of integrated circuits (ICs) may include front-end-of-line (FEOL), middle of line (MOL), and back-end-of-line (BEOL) processes. The FEOL process may include wafer preparation, isolation, well formation, gate patterning, spacer, extension and source/drain implantation, silicide formation, and dual stress liner formation. The MOL process may include gate contact formation. Middle of line layers may include, but are not limited to, MOL contacts, vias or other layers within close proximity to the semiconductor device transistors or other like active devices. The BEOL processes may include a series of wafer processing steps for interconnecting the semiconductor devices created during the FEOL and MOL processes. Successful fabrication of modern semiconductor chip products involves an interplay between the materials and the processes employed.
Various challenges arise when designing an advanced node at or below, for example, sixteen (16) nanometers. For example, reducing die size is important for containing cost while improving yield due to the advanced node scaling. Passives and input/output (I/O) devices may take up significant space on the die of a system on chip (SoC). Although the passives and I/O devices increase the die size, these devices may not involve advanced node processing, and thus become a source of added cost and complexity. For example, at ten (10) nanometers, suppliers are debating whether to include 1.8 volt (V) I/O devices in their technology offerings. Unfortunately, many I/O technologies continue to operate at 1.8 V.